The present invention generally relates to semiconductor devices and more particularly to a miniaturized semiconductor device and a fabrication process thereof in which leakage current is minimized.
With the continuous progress of device miniaturization, the integration density of semiconductor integrated circuit devices, particularly the integration density of memory semiconductor integrated circuit devices, is increasing every year. These days, intensive investigations are being made on so-called sub-halfmicron devices having a minimum pattern width of 0.3 xcexcm or less.
In a DRAM (dynamic random access memory) that stores information in a memory cell capacitor in the form of electric charges, the device miniaturization inevitably causes a decrease in the capacitance of the memory cell capacitor, and there is a tendency that the retention of information in the memory cell capacitor becomes unstable. Further, the read/write operation may become also unstable in such extremely miniaturized DRAMs. Similar problem occurs also in so-called flash memory devices in which information is stored in a floating gate in the form of electric charges. Thus, various efforts are being made for stabilizing the operation of the miniaturized DRAMs and flash memories.
FIGS. 1A-1F show a conventional fabrication process of a DRAM.
Referring to FIG. 1A, an active region is defined on a Si substrate 1 typically doped to the p-type, by providing a field oxide film 2A of SiO2 on the Si substrate 1, and a thin thermal oxide film 2B also of SiO2 is formed on the active region thus defined on the Si substrate 1 by the field oxide film 2A. Further, a word line WL of polysilicon is provided on the Si substrate 1 so as to extend over the substrate 1 thus covered by the field oxide film 2A and further the thermal oxide film 2B, wherein the word line WL extends over the thermal oxide film 2B in the active region and the word line WL thus extending over the thermal oxide film 2B forms a gate electrode of a memory cell transistor. Thereby, the thermal oxide film 2B forms a gate insulation film of the memory cell transistor.
In the step of FIG. 1A, an ion implantation process of P+ is conducted further into the Si substrate 1 while using the gate electrode 3 as a self-aligned mask, and there are formed diffusion regions 1A and 1B of the memory cell transistor in the Si substrate 1 at both lateral sides of the gate electrode 3.
Next, in the step of FIG. 1B, an oxide film 4 of SiO2 is deposited on the structure of FIG. 1A by a high temperature CVD process so as to cover the gate electrode 3, and an anisotropic etching process acting generally perpendicularly to a principal surface of the substrate 1 is applied to the thermal oxide film 4 in the step of FIG. 1C by an RIE (reactive ion etching) process, to form side wall oxide films 4A and 4B covering both side walls of the gate electrode 3. In the step of FIG. 1C, it is also possible, while not illustrated, to conduct an ion implantation process of P+ while using the gate electrode 3 and further the side wall oxide films 4A and 4B as a self-aligned mask, to form a so-called LDD (lightly-doped drain) structure.
Next, in the step of FIG. 1D, an interlayer insulation film 5 of BPSG (borophosophosilicate glass) is deposited on the structure of FIG. 1C, followed by a formation of a contact hole 5A in the interlayer insulation film 5 so as to expose the diffusion region 1A. Further, an electrode 6 is provided as a part of a bit line such that the electrode 6 fills the contact hole 5A and achieves an electrical contact to the exposed diffusion region 1A.
Further, in the step of FIG. 1E, another interlayer insulation film 7 of BPSG is deposited on the structure of FIG. 1D, followed by a formation of a contact hole 7A penetrating through the interlayer insulation films 7 and 5 such that the contact hole 7A exposes the foregoing diffusion region 1B.
Finally, in the step of FIG. 1F, an accumulation electrode pattern 8A of polysilicon is formed so as to fill the contact hole 7A in electrical contact with the diffusion region 1B, and a dielectric film 8B having a so-called ONO structure, in which a thin SiN film is vertically sandwiched by a pair of thin SiO2 films, is provided so as to cover the accumulation electrode 8A. Further, an opposing electrode 8C of polysilicon is provided so as to cover the foregoing dielectric film 8B. Thereby, the electrode 8A, the dielectric film 8B and the opposing electrode 8C form together a memory cell capacitor 8.
In the DRAM of the foregoing conventional structure, it has been discovered that there are cases in which a leakage current flows between the accumulation electrode pattern 8A and the gate electrode 3 when the DRAM is miniaturized particularly to the degree in which the minimum pattern width is 0.3 xcexcm or less. As the accumulation electrode 8A forms a part of the memory cell capacitor 8 that holds the information in the form of electric charges, the leakage current occurring in the electrode 8A causes a serious problem in the operation of the DRAM, particularly the stability of data retention.
FIG. 2A shows a part of the DRAM of FIG. 1F in an enlarged scale.
Referring to FIG. 2A, it can be seen that the gate electrode 3 carries an anti-reflection film 3A that has been used for patterning the gate electrode 3. Further, a CVD oxide film 5B is provided between the side wall oxide film 4A or 4B and the interlayer insulation film 5. In order to secure a sufficient distance between the gate electrode 3 and the electrode 8A in the contact hole 5A, the contact hole 5A is formed to have a tapered structure in which the diameter reduces gradually from a top surface to a bottom surface of the contact hole 5A.
In such sub-halfmicron DRAMs having a minimum pattern width of 0.3 xcexcm or less, it is actually difficult to form the contact hole 5A in the ideally aligned state as shown in FIG. 2A, and actual devices generally have a structure shown in FIG. 2B, in which it will be noted that the contact hole 5A is offset from the ideal state of FIG. 2A. In the structure of FIG. 2B, the accumulation electrode 8A filling the contact hole 5A approaches the gate electrode 3, and it is believed that such a reduction in the distance between the gate electrode 3 and the electrode 8A causes the leakage current to flow between the accumulation electrode 8A and the gate electrode 3, although the exact current path of the leakage current is not fully explored yet.
As will be explained later, the problem of leakage current appears particularly conspicuous when an etching is applied to the diffusion region 1B by a buffered HF solution for removing a native oxide film from the surface of the diffusion region 1B.
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a fabrication process thereof wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a semiconductor device having a gate electrode in which leakage current to the gate electrode from an opposing electrode is successfully minimized, as well as a fabrication process thereof.
Another object of the present invention is to provide a semiconductor device, comprising:
a substrate;
a gate electrode provided on said substrate;
a side wall insulation film covering a side wall of said gate electrode;
a diffusion region formed in said substrate adjacent to said gate electrode;
an ohmic electrode formed on said diffusion region; and
a nitride film provided between said side wall insulation film and said wall of said gate electrode, such that said nitride film covers a part of a surface of said gate electrode facing said ohmic electrode.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:
forming a gate electrode on a substrate;
forming a diffusion region in said substrate adjacent to said gate electrode;
forming a side wall insulation film on a side wall of said gate electrode;
depositing an interlayer insulation film on said gate electrode provided with said side wall insulation film;
forming a contact hole in said interlayer insulation film so as to expose a surface of said diffusion region; and
forming an ohmic electrode so as to fill said contact hole;
wherein said method further comprises a step, before said step of depositing said interlayer insulation film, of depositing a nitride film such that said nitride film covers at least a part of said gate electrode that faces said ohmic electrode.
According to the present invention, the leakage current path between the gate electrode and the ohmic electrode is successfully interrupted by providing the nitride film such that the nitride film covers a part of the gate electrode that faces the ohmic electrode.
Another object of the present invention is to provide a DRAM, comprising:
a substrate;
a gate electrode provided on said substrate and forming a part of a word line;
a pair of side wall insulation films covering both lateral side walls of said gate electrode;
first and second diffusion regions formed in said substrate at both lateral sides of said gate electrode;
a first interlayer insulation film covering said gate electrode including said pair of side wall insulation films;
a first contact hole formed in said first interlayer insulation film so as to expose said first diffusion region;
a first electrode provided on said first interlayer insulation film so as to fill said first contact hole in contact with said first diffusion region, said first electrode thereby forming a part of a bit line;
a second interlayer insulation film provided on said first interlayer insulation film so as to cover said first electrode;
a second contact hole formed in said second interlayer insulation film so as to penetrate through said first interlayer insulation film, said second contact hole exposing said second diffusion region;
a second electrode provided on said second interlayer insulation film so as to fill said second contact hole in contact with said second diffusion region, said second electrode thereby forming an accumulation electrode of a memory cell capacitor;
a dielectric film provided on a surface of said second electrode as a capacitor electrode of said memory cell capacitor;
a third electrode provided on said dielectric film so as to sandwich said dielectric film therebetween together with said second electrode, said third electrode thereby forming an opposing electrode of said memory cell capacitor; and
a nitride film provided so as to cover at least a part of said gate electrode that faces said accumulation electrode.
Another object of the present invention is to provide a method of fabricating a DRAM, comprising the steps of:
forming a gate electrode on a substrate;
forming first and second diffusion regions in said substrate respectively adjacent to a first side wall and a second side wall of said gate electrode;
forming first and second side wall insulation films respectively on said first and second side walls of said gate electrode;
depositing a first interlayer insulation film such that said first interlayer insulation film covers said gate electrode and said first and second side wall insulation films;
forming a first contact hole in said first interlayer insulation film such that said first contact hole exposes said first diffusion region;
forming a bit line pattern on said first interlayer insulation film such that said bit line pattern fills said first contact hole in contact with said first diffusion region;
forming a second interlayer insulation film on said first interlayer insulation film such that said second interlayer insulation film fills said bit line pattern;
forming a second contact hole in said second interlayer insulation film such that said second contact hole penetrates through said first interlayer insulation film and exposes said second diffusion region;
forming an accumulation electrode of a memory cell capacitor such that said accumulation electrode fills said second contact hole and achieves an electrical contact with said second diffusion region;
forming a capacitor insulation film on said accumulation electrode; and
forming an opposing electrode on said capacitor electrode;
wherein said method further includes a step, after said step of forming said gate electrode but before said step of forming said first interlayer insulation film, of depositing a nitride film such that said nitride film covers a part of said gate electrode facing said accumulating electrode.
According to the present invention, the current path of the leakage current between the accumulating electrode and the gate electrode is interrupted by providing the nitride film, and the problem of loss of information caused by the dissipation of the electric charges held in the accumulating electrode of the memory cell capacitor is successfully eliminated. Thereby, the DRAM shows an excellent stability of data retention even when the device is miniaturized to a sub-halfmicron size.
Another object of the present invention is to provide a flash memory, comprising:
a substrate;
a gate electrode structure provided on said substrate, said gate electrode structure including: a floating electrode provided on said substrate, said floating electrode being isolated from said substrate by a tunnel insulation film intervening therebetween; and a control electrode provided on said floating electrode with a floating insulation film intervening between said control electrode and said floating electrode, said control electrode thereby forming a part of a word line, said gate electrode structure being defined by a pair of side walls;
a pair of side wall insulation films respectively covering said pair of side walls of said gate electrode structure;
first and second diffusion regions formed in said substrate at both lateral sides of said gate electrode structure;
an interlayer insulation film covering said gate electrode structure including said pair of side wall insulation films;
first and second contact holes formed in said interlayer insulation film so as to expose said first and second diffusion regions respectively;
a first electrode provided on said interlayer insulation film so as to fill said first contact hole in contact with said first diffusion region, said first electrode thereby forming a part of a bit line;
a second electrode provided on said interlayer insulation film so as to fill said second contact hole in contact with said second diffusion region; and
a nitride film provided on said gate electrode structure so as to cover at least one of said side walls such that said nitride film intervenes between said wall of said gate electrode structure and corresponding said side wall insulation film.
Another object of the present invention is to provide a method of fabricating a flash memory, comprising the steps of:
forming a tunnel insulation film on a substrate;
forming a gate structure by depositing a floating gate electrode, a floating insulation film and a control gate consecutively on said tunnel insulation film;
forming a diffusion region in said substrate while using said gate structure as a mask;
depositing an interlayer insulation film on said substrate such that said interlayer insulation film covers said gate structure;
forming a contact hole in said interlayer insulation film such that said contact hole exposes said diffusion region; and
forming an ohmic electrode on said interlayer insulation film such that said ohmic electrode fills said contact hole in contact with said diffusion region;
wherein said method further comprises a step, after said step of forming said gate electrode but before said step of depositing said interlayer insulation film, of forming a nitride film on said gate structure such that said nitride film covers at least a part of said gate structure facing said electrode.
According to the present invention, the problem of leakage of electric charges from the floating electrode of the gate structure is successfully eliminated by interrupting the leakage current path by providing the nitride film on the side wall of the gate structure.
Another object of the present invention is to provide a semiconductor device comprising:
a substrate,
a gate electrode formed on said substrate;
a diffusion region formed in said substrate adjacent to said gate electrode;
an ohmic electrode contacting said diffusion region; and
a side wall insulation film formed on a side wall of said gate electrode;
said side wall comprising a first insulation film contacting said side wall of said gate electrode at a side thereof facing said ohmic electrode, and a second insulation film formed on said first insulation film.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising:
forming a gate electrode on a substrate;
forming a diffusion region in said substrate adjacent to said gate electrode;
forming a side wall insulation film on a side wall of said gate electrode;
depositing an interlayer insulation film on said gate electrode formed with said side wall insulation film;
forming a contact hole in said interlayer insulation film such that said contact hole exposes said diffusion region; and
forming an ohmic electrode such that said ohmic electrode fills said contact hole in electrical contact with said diffusion region;
wherein said step of forming said side wall insulation film comprises the steps of:
forming a first insulation film on said gate electrode such that said first insulation film covers said gate electrode including said side wall;
applying a first anisotropic etching process to said first insulation film such that said first anisotropic etching process proceeds generally perpendicularly to a principal surface of said substrate, a remaining part of said first insulation film forming thereby a first side wall insulation film covering said side wall of said gate electrode;
forming a second insulation film on said gate electrode such that said second insulation film covers said gate electrode including said first side wall insulation film;
applying a second anisotropic etching process to said second insulation film such that said second anisotropic etching process proceeds generally perpendicularly to said principal surface of said substrate, a remaining part of said second insulation film forming thereby a second side wall insulation film covering said first side wall insulation film laterally.
Another object of the present invention is to provide a method of fabricating a semiconductor memory device, comprising the steps of:
forming a gate electrode on a substrate;
forming first and second diffusion regions in said substrate respectively adjacent to first and second side walls of said gate electrode;
forming first and second side wall insulation films respectively on said first and second side walls of said gate electrode;
forming a first interlayer insulation film on said gate electrode such that said first interlayer insulation film covers said first and second side wall insulation films;
forming a first contact hole in said first interlayer insulation film such that said first contact hole exposes said first diffusion region;
forming a bit line pattern on said first interlayer insulation film so as to fill said first contact hole in electrical contact with said first diffusion region;
forming a second interlayer insulation film on said first interlayer insulation film so as to cover said bit line pattern;
forming a second contact hole in said second interlayer insulation film such that said second contact hole penetrates through said first interlayer insulation film and exposes said second diffusion region;
forming an accumulation electrode of a memory cell capacitor such that said accumulation electrode fills said second contact hole and contacts said second diffusion region;
forming a capacitor dielectric film on said accumulation electrode; and
forming an opposing electrode on said capacitor dielectric film,
wherein said step of forming said first and second side wall insulation films includes the steps of:
depositing a first insulation film on said gate electrode such that said first insulation film covers said first and second side walls of said gate electrode;
applying a first anisotropic etching process proceeding generally perpendicularly to a principal surface of said substrate, to said first insulation film to form first and second, lower side wall insulation films respectively on said first and second side walls of said gate electrode in an intimate contact therewith;
depositing a second insulation film on said gate electrode such that said second insulation film covers said first and second lower side wall insulation films; and
applying a second anisotropic etching process proceeding generally perpendicularly to said principal surface of said substrate, to said second insulation film to form first and second, upper side wall insulation films respectively on said first and second lower side wall insulation films.
According to the present invention, the leakage current from the gate electrode is suppressed successfully by forming the side wall insulation film of the gate electrode by two different side wall insulation films.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.